Senior Level Verification Engineer


Senior Level Verification Engineer

The role is for the fast-growing CPU Hardware team.

You will

  • Be responsible for the delivery of all verification activities related to a CPU component or sub-system from early stages of verification planning to sign-off
  • Create verification plans, develop and maintain testbench components,
  • Track and report verification metrics and closure
  • Participate in all stages of design specification definition providing feedback from the verification perspective
  • Be responsible for the definition, effort estimation and tracking of your own work
  • Be able to influence and advance our CPU verification methodology
  • Have the opportunity to lead, coach and mentor other members of the team
  • Participate in design and verification reviews and recommend improvements
  • Contribute to team shared knowledge via open discussions and presentations

Required skills:

  • Have a proven track record of developing verification environments for complex RTL designs
  • Have excellent understanding of constrained-random verification methodology and challenges of verification closure
  • Be confident in defining verification requirements, and work out the implementation approach and details of a testbench
  • Be able to do root-cause analysis of complex issues and resolve them in a timely manner
  • Have excellent knowledge of SystemVerilog and UVM
  • Be able to develop new verification flows
  • Have working knowledge of ASIC design methodologies, flows and tools
  • Be able to plan, estimate and track your own work


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